1) Field of the Invention
This invention relates generally to a semiconductor device and a method of fabrication of the same, more specifically this invention relates to a semiconductor device and method of the same to reduce source/drain to substrate junction capacitance.
2) Description of the Related Art
The evolution of MOSFET technology has been governed by device scaling for high performance of the transistor. Partially-depleted SOI (PDSOI) has become one of the promising solutions for high performance sub-100 nm gate length CMOS due to the inherent advantages of a higher drain saturation current and reduced junction capacitance. However there are problems associated with PDSOI CMOS devices. These include wafer cost, history effect and self heating effect.
The following patents and literature are relevant technical art.
U.S. Pat. No. 6,383,883B1 (Chen et al.) that shows a graded S/D region.
U.S. Pat. No. 6,348,372B1 (Burr) shows a method to reduce S/D junction capacitance.
U.S. 2003/0132452 A1 (Boriuchi) shows a recombination region below and adjoining the S/D.
U.S. Pat. No. 5,795,803 (Takamura et al.) shows a multi-level/concentration well process.
U.S. Pat. No. 6,528,826 B2 (Yoshida et al.) shows a depletion type device.
U.S. 2002-009364A1 (Inaba) shows a method to form a SODEL device.
U.S. Pat. No. 5,712,204 (Horiuchi) shows a method to reduce S/D junction capacitance.
U.S. Pat. No. 5,712,204 shows a method of making a semiconductor device having reduced junction capacitance between the source and drain regions and the substrate.
Inaba et al., Article entitled: Method of forming an artificial depletion layer below source/drain and Channel of the MOSFET to reduce junction capacitance (SODEL FET), IEDM 2002, Toshiba.
However, there is a need for improved devices.